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copyright ? 2002/2003 solomon systech limited. rev 1.4 01/03 this document contains information on a new product. specifications and information herein are subject to change without notice. ssd1820a ssd1821 ordering information ssd1820az gold bump die ssd1821z gold bump die ssd1820atr1 tab SSD1821TR1 tab gold bump die tab solomon systech semiconductor technical data advance information lcd segment / common driver with controller cmos ssd1820a/21 is a single-chip cmos lcd driver with controller for a liquid crystal dot-matrix graphic display system. ssd1820a consists of 194 high voltage driving out- put pins for driving 128 segments, 64 commons and 2 icon driving commons, while ssd1821 consists of 210 high voltage driving output pins for driving 128 segments, 80 commons and 2 icon driving commons. ssd1820a/21 displays data directly from its internal 128x65/128x81 bits graphic display data ram (gddram). data/commands are sent from general mcu through a hardware selectable 6800-/8080-series compatible parallel interface or 3/4 wires serial peripheral interface. ssd1820a/21 embeds a dc-dc converter, a lcd voltage regulator, an on- chip bias divider and an on-chip oscillator which reduce the number of external components. with the special design on minimizing power consumption and die/pack- age layout, ssd1820a/21 is suitable for any portable battery-driven applications re- quiring a long operation period and a compact size. ? 128 x 64/80 graphic display with a icon line ? programmable multiplex ratio [16mux - 65mux/81mux] (partial display) ? single supply operation, 1.8 v - 3.3v ? low current sleep mode(<1.0ua) ? on-chip voltage generator / external power supply ? software selectable 2x / 3x / 4x / 5x / 6x on-chip dc-dc converter ? on-chip oscillator ? software selectable on-chip bias dividers ? programmable 1/4, 1/5, 1/6, 1/7, 1/8, 1/9 and 1/10 bias ratio ? maximum +15.0v lcd driving output voltage ? hardware pin selectable for 8-bit 6800-series parallel interface , 8-bit 8080-series par- allel interface, 3-wire serial peripheral interface or 4-wire serial peripheral interface ? on-chip 128 x 65/81 graphic display data ram ? re-mapping of row and column drivers ? vertical scrolling ? display offset control ? 64 levels internal contrast control ? external contrast control ? maximum 17mhz spi or 15mhz ppi operation ? selectable lcd driving voltage temperature coefficients (2 settings) ? available in gold bump die and standard tab (tape automated bonding) package
ssd1820a/21 2 rev 1.4 01/03 solomon lcd driving voltage generator 2x / 3 x / 4 x / 5x /6x dc/dc converter, voltage regulator, bias divider, contrast control, temperature compensation com 0 to com63/79 seg0~seg 127 v ss v dd d 7 vl6 v cc v r gddram 1 28 x 65 bits (ssd1820a) 128 x 81 bits (ssd1821) command decoder parallel / serial interface command interface display timing generator 1 93 bit latch (ssd1820a) 209 bit latch (ssd 1821) hv buffer cell level shifter level selector oscillator d 6 d 5 d 4 d 3 d 2 d 1 d 0 (sda) (sck) v ss block diagram icons ref intrs v ci c 1p c 2p c 3p c 4p c 1n c 2n v ext res ps0 ps1 cs d/ c r/ w e vl5 vl4 vl3 vl2 ( wr ) ( rd ) c 5p cl
solomon ssd1820a/21 3 rev 1.4 01/03 ssd1820atr pin assignment (copper view) n/c ps1 /cs /res d/c r/w (/wr) e (/rd) d0 d1 d2 d3 d4 d5 d6 d7 vdd vss vcc c3p c1n c1p c2p c2n nc vl2 vl3 vl4 vl5 vl6 vr cl n/c n/c n/c n/c icons com63 com62 : : : : : : com33 com32 n/c seg127 seg126 : : : : : : seg1 seg0 icons com0 com1 : : : : : : com29 com30 com31 n/c n/c n/c 233 232 231 230 229 228 199 198 197 196 195 70 69 68 67 66 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ssd1820at pin assignment (copper view) note : ps0, ref, intrs and vci are connected to vdd set condition: parallel interface, internal reference voltage, internal voltage regulator and booster reference voltage is vdd
ssd1820a/21 4 rev 1.4 01/03 solomon ssd1821t pin assignment (copper view) n/c cl vr vl6 vl5 vl4 vl3 vl2 intrs c4p c2n c2p c1p c1n c3p c5p vcc vss vci vdd d7(sda) d6(sck) d5 d4 d3 d2 d1 d0 e (/rd) r/w (/wr) d/c /res /cs ps1 ps0 n/c n/c com39 com38 com37 com36 : : : : : : com1 com0 icons seg0 seg1 : : : : : : seg125 seg126 seg127 com40 com41 : : : : : : com75 com76 com77 com78 com79 icons 247 246 245 244 243 208 207 206 205 204 80 79 78 77 76 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 note : ref connected to vdd
solomon ssd1820a/21 5 rev 1.4 01/03 n/c n/c : n/c cl vss vr vr vl6 vl6 vl6 vl5 vl5 vl5 vl4 vl4 vl4 vl3 vl3 vl3 vl2 vl2 vl2 vss intrs vdd vext ref vss c4p c4p c4p c2n c2n c2n c2n c2p c2p c2p c1p c1p c1p c1n c1n c1n c1n c3p c3p c3p n/c n/c n/c vcc vcc vcc vcc vss vss vss vss vss vss vci vci vci vci vci vdd vdd vdd d7 (sda) d7 (sda) d6 (sck) d6 (sck) d5 d4 d3 d2 d1 d0 vdd e(/rd) e(/rd) r/w(/wr) r/w(/wr) vss d/c d/c d/c /res vdd /cs /cs vss ps1 vdd vss ps0 vdd n/c n/c : : n/c n/c com5 com4 com3 com2 com1 com0 icons seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : seg113 seg114 seg115 seg116 seg117 seg118 seg119 seg120 seg121 seg122 seg123 seg124 seg125 seg126 seg127 com32 com33 com34 com35 com36 com37 com38 n / c c o m 3 9 c o m 4 0 c o m 4 1 c o m 4 2 : : : : : : : : : : : c o m 6 1 c o m 6 2 c o m 6 3 i c o n s n / c die size: 10.8mm x 1.96mm : : : 1 115 144 285 die thickness: 534um +/- 25um note: 1. diagram showing the face of the die. 2. coordinates are reference to center of the chip. 3. unit of coordinates and size of all alignment marks are in um. 4. all alignment keys do not contain gold bump. x y ( 0 , 0 ) bump height: 18um +/- 3um ssd1820az die pin assignment n / c c o m 6 c o m 7 c o m 8 c o m 9 : : : : : : : : : : : c o m 2 8 c o m 2 9 c o m 3 0 c o m 3 1 n / c pin#1 drawing not to scale
ssd1820a/21 6 rev 1.4 01/03 solomon com32 : com39 cl vss vr vr vl6 vl6 vl6 vl5 vl5 vl5 vl4 vl4 vl4 vl3 vl3 vl3 vl2 vl2 vl2 vss intrs vdd vext ref vss c4p c4p c4p c2n c2n c2n c2n c2p c2p c2p c1p c1p c1p c1n c1n c1n c1n c3p c3p c3p c5p c5p c5p vcc vcc vcc vcc vss vss vss vss vss vss vci vci vci vci vci vdd vdd vdd d7 (sda) d7 (sda) d6 (sck) d6 (sck) d5 d4 d3 d2 d1 d0 vdd e(/rd) e(/rd) r/w(/wr) r/w(/wr) vss d/c d/c d/c /res vdd /cs /cs vss ps1 vdd vss ps0 vdd n/c n/c n/c n/c icons com79 : com73 com5 com4 com3 com2 com1 com0 icons seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : seg113 seg114 seg115 seg116 seg117 seg118 seg119 seg120 seg121 seg122 seg123 seg124 seg125 seg126 seg127 com40 com41 com42 com43 com44 com45 com46 n / c c o m 4 7 c o m 4 8 c o m 4 9 c o m 5 0 : : : : : : : : : : : c o m 6 9 c o m 7 0 c o m 7 1 c o m 7 2 n / c die size: 10.8mm x 1.96mm : : 1 115 144 285 die thickness: 534um +/- 25um note: 1. diagram showing the face of the die. 2. coordinates are reference to center of the chip. 3. unit of coordinates and size of all alignment marks are in um. 4. all alignment keys do not contain gold bump. x y ( 0 , 0 ) bump height: 18um +/- 3um ssd1821z die pin assignment n / c c o m 6 c o m 7 c o m 8 c o m 9 : : : : : : : : : : : c o m 2 8 c o m 2 9 c o m 3 0 c o m 3 1 n / c pin#1 drawing not to scale
solomon ssd1820a/21 7 rev 1.4 01/03 pin#1 (0,0) x y 67.5um 22.5um 22.5um 22.5um center ( - 3926.1, 120) x 22.5um 67.5um center (3991.5, 120) x 99.9um 99.9um center (4409.4, - 147.9) x 78.75um 18.9um 78.75um x center ( - 4095, - 64.65) center (4263, - 64.65) center (4515.6, - 148.05) 70.875um 100.2um 52.2um 10.65um 51.9um 99.9um 49.8um 50.1um 10.98um 58.35um x 2. coordinates are reference to center of the chip 3. unit of coordinates and size of all alignment marks are in um. 4. all alignment keys do not contain gold bmup. 5. ?x? represents the center point. 6. drawing not to scale notes: 1. diagram showing the gold bump view of the die. ssd1820az & ssd1821z alignment key position
ssd1820a/21 8 rev 1.4 01/03 solomon ssd1820a/21z die pad coordinates pad# ssd1820a ssd1821 x-pos y-pos pad# ssd1820a ssd1821 x-pos y-pos pad# ssd1820a ssd1821 x-pos y-pos pad# ssd1820a ssd1821 x-pos y-pos 1 n/c com73 -4568.40 -773.40 116 n/c n/c 5191.50 -874.80 144 com5 com5 4568.40 773.40 286 n/c n/c -5191.50 874.80 2 n/c com74 -4503.60 -773.40 117 com31 com31 5191.50 -810.00 145 com4 com4 4503.60 773.40 287 com39 com47 -5191.50 810.00 3 n/c com75 -4438.80 -773.40 118 com30 com30 5191.50 -745.20 146 com3 com3 4438.80 773.40 288 com40 com48 -5191.50 745.20 4 n/c com76 -4374.00 -773.40 119 com29 com29 5191.50 -680.40 147 com2 com2 4374.00 773.40 289 com41 com49 -5191.50 680.40 5 n/c com77 -4309.20 -773.40 120 com28 com28 5191.50 -615.60 148 com1 com1 4309.20 773.40 290 com42 com50 -5191.50 615.60 6 n/c com78 -4244.40 -773.40 121 com27 com27 5191.50 -550.80 149 com0 com0 4244.40 773.40 291 com43 com51 -5191.50 550.80 7 n/c com79 -4179.60 -773.40 122 com26 com26 5191.50 -486.00 150 icons icons 4179.60 773.40 292 com44 com52 -5191.50 486.00 8 n/c icons -4114.80 -773.40 123 com25 com25 5191.50 -421.20 151 seg0 seg0 4114.80 773.40 293 com45 com53 -5191.50 421.20 9 nc nc -3964.80 -807.45 124 com24 com24 5191.50 -356.40 152 seg1 seg1 4050.00 773.40 294 com46 com54 -5191.50 356.40 10 nc nc -3887.40 -807.45 125 com23 com23 5191.50 -291.60 153 seg2 seg2 3985.20 773.40 295 com47 com55 -5191.50 291.60 11 nc nc -3810.00 -807.45 126 com22 com22 5191.50 -226.80 154 seg3 seg3 3920.40 773.40 296 com48 com56 -5191.50 226.80 12 nc nc -3732.60 -807.45 127 com21 com21 5191.50 -162.00 155 seg4 seg4 3855.60 773.40 297 com49 com57 -5191.50 162.00 13 vdd vdd -3634.28 -807.45 128 com20 com20 5191.50 -97.20 156 seg5 seg5 3790.80 773.40 298 com50 com58 -5191.50 97.20 14 ps0 ps0 -3558.08 -807.45 129 com19 com19 5191.50 -32.40 157 seg6 seg6 3726.00 773.40 299 com51 com59 -5191.50 32.40 15 vss vss -3481.88 -807.45 130 com18 com18 5191.50 32.40 158 seg7 seg7 3661.20 773.40 300 com52 com60 -5191.50 -32.40 16 vdd vdd -3405.68 -807.45 131 com17 com17 5191.50 97.20 159 seg8 seg8 3596.40 773.40 301 com53 com61 -5191.50 -97.20 17 ps1 ps1 -3329.48 -807.45 132 com16 com16 5191.50 162.00 160 seg9 seg9 3531.60 773.40 302 com54 com62 -5191.50 -162.00 18 vss vss -3253.28 -807.45 133 com15 com15 5191.50 226.80 161 seg10 seg10 3466.80 773.40 303 com55 com63 -5191.50 -226.80 19 /cs /cs -3177.08 -807.45 134 com14 com14 5191.50 291.60 162 seg11 seg11 3402.00 773.40 304 com56 com64 -5191.50 -291.60 20 /cs /cs -3100.88 -807.45 135 com13 com13 5191.50 356.40 163 seg12 seg12 3337.20 773.40 305 com57 com65 -5191.50 -356.40 21 vdd vdd -3024.68 -807.45 136 com12 com12 5191.50 421.20 164 seg13 seg13 3272.40 773.40 306 com58 com66 -5191.50 -421.20 22 /res /res -2948.48 -807.45 137 com11 com11 5191.50 486.00 165 seg14 seg14 3207.60 773.40 307 com59 com67 -5191.50 -486.00 23 d/c d/c -2872.28 -807.45 138 com10 com10 5191.50 550.80 166 seg15 seg15 3142.80 773.40 308 com60 com68 -5191.50 -550.80 24 d/c d/c -2796.08 -807.45 139 com9 com9 5191.50 615.60 167 seg16 seg16 3078.00 773.40 309 com61 com69 -5191.50 -615.60 25 d/c d/c -2719.88 -807.45 140 com8 com8 5191.50 680.40 168 seg17 seg17 3013.20 773.40 310 com62 com70 -5191.50 -680.40 26 vss vss -2643.68 -807.45 141 com7 com7 5191.50 745.20 169 seg18 seg18 2948.40 773.40 311 com63 com71 -5191.50 -745.20 27 r/w r/w -2567.48 -807.45 142 com6 com6 5191.50 810.00 170 seg19 seg19 2883.60 773.40 312 icons com72 -5191.50 -810.00 28 r/w r/w -2491.28 -807.45 143 n/c n/c 5191.50 874.80 171 seg20 seg20 2818.80 773.40 313 n/c n/c -5191.50 -874.80 29 e e -2415.08 -807.45 172 seg21 seg21 2754.00 773.40 30 e e -2338.88 -807.45 173 seg22 seg22 2689.20 773.40 31 vdd vdd -2262.68 -807.45 174 seg23 seg23 2624.40 773.40 32 d0 d0 -2186.48 -807.45 175 seg24 seg24 2559.60 773.40 33 d1 d1 -2110.28 -807.45 176 seg25 seg25 2494.80 773.40 34 d2 d2 -2034.08 -807.45 177 seg26 seg26 2430.00 773.40 35 d3 d3 -1957.88 -807.45 178 seg27 seg27 2365.20 773.40 36 d4 d4 -1881.68 -807.45 179 seg28 seg28 2300.40 773.40 37 d5 d5 -1805.48 -807.45 180 seg29 seg29 2235.60 773.40 38 d6 d6 -1729.28 -807.45 181 seg30 seg30 2170.80 773.40 39 d6 d6 -1653.08 -807.45 182 seg31 seg31 2106.00 773.40 40 d7 d7 -1576.88 -807.45 183 seg32 seg32 2041.20 773.40 41 d7 d7 -1500.68 -807.45 184 seg33 seg33 1976.40 773.40 42 vdd vdd -1424.48 -807.45 185 seg34 seg34 1911.60 773.40 43 vdd vdd -1348.28 -807.45 186 seg35 seg35 1846.80 773.40 44 vdd vdd -1272.08 -807.45 187 seg36 seg36 1782.00 773.40 45 vci vci -1149.90 -780.75 188 seg37 seg37 1717.20 773.40 46 vci vci -1073.70 -780.75 189 seg38 seg38 1652.40 773.40 47 vci vci -997.50 -780.75 190 seg39 seg39 1587.60 773.40 48 vci vci -921.30 -780.75 191 seg40 seg40 1522.80 773.40 49 vci vci -845.10 -780.75 192 seg41 seg41 1458.00 773.40 50 vss vss -768.90 -780.75 193 seg42 seg42 1393.20 773.40 51 vss vss -692.70 -780.75 194 seg43 seg43 1328.40 773.40 52 vss vss -616.50 -780.75 195 seg44 seg44 1263.60 773.40 53 vss vss -540.30 -780.75 196 seg45 seg45 1198.80 773.40 54 vss vss -464.10 -780.75 197 seg46 seg46 1134.00 773.40 55 vss vss -387.90 -780.75 198 seg47 seg47 1069.20 773.40 56 vcc vcc -311.70 -780.75 199 seg48 seg48 1004.40 773.40 57 vcc vcc -230.40 -780.75 200 seg49 seg49 939.60 773.40 58 vcc vcc -149.10 -780.75 201 seg50 seg50 874.80 773.40 59 vcc vcc -67.80 -780.75 202 seg51 seg51 810.00 773.40 60 nc c5p 13.50 -780.75 203 seg52 seg52 745.20 773.40 61 nc c5p 94.80 -780.75 204 seg53 seg53 680.40 773.40 62 nc c5p 176.10 -780.75 205 seg54 seg54 615.60 773.40 63 c3p c3p 257.40 -780.75 206 seg55 seg55 550.80 773.40 64 c3p c3p 338.70 -780.75 207 seg56 seg56 486.00 773.40 65 c3p c3p 420.00 -780.75 208 seg57 seg57 421.20 773.40 66 c1n c1n 536.70 -780.75 209 seg58 seg58 356.40 773.40 67 c1n c1n 612.90 -780.75 210 seg59 seg59 291.60 773.40 68 c1n c1n 689.10 -780.75 211 seg60 seg60 226.80 773.40 69 c1n c1n 765.30 -780.75 212 seg61 seg61 162.00 773.40 70 c1p c1p 882.00 -780.75 213 seg62 seg62 97.20 773.40 71 c1p c1p 963.30 -780.75 214 seg63 seg63 32.40 773.40
solomon ssd1820a/21 9 rev 1.4 01/03 ssd1820a/21z die pad coordinates 72 c1p c1p 1044.60 -780.75 215 seg64 seg64 -32.40 773.40 73 c2p c2p 1125.90 -780.75 216 seg65 seg65 -97.20 773.40 74 c2p c2p 1207.20 -780.75 217 seg66 seg66 -162.00 773.40 75 c2p c2p 1288.50 -780.75 218 seg67 seg67 -226.80 773.40 76 c2n c2n 1405.20 -780.75 219 seg68 seg68 -291.60 773.40 77 c2n c2n 1481.40 -780.75 220 seg69 seg69 -356.40 773.40 78 c2n c2n 1557.60 -780.75 221 seg70 seg70 -421.20 773.40 79 c2n c2n 1633.80 -780.75 222 seg71 seg71 -486.00 773.40 80 c4p c4p 1750.50 -780.75 223 seg72 seg72 -550.80 773.40 81 c4p c4p 1831.80 -780.75 224 seg73 seg73 -615.60 773.40 82 c4p c4p 1913.10 -780.75 225 seg74 seg74 -680.40 773.40 83 vss vss 1989.30 -780.75 226 seg75 seg75 -745.20 773.40 84 ref ref 2065.50 -780.75 227 seg76 seg76 -810.00 773.40 85 vext vext 2182.20 -780.75 228 seg77 seg77 -874.80 773.40 86 vdd vdd 2258.40 -780.75 229 seg78 seg78 -939.60 773.40 87 intrs intrs 2334.60 -780.75 230 seg79 seg79 -1004.40 773.40 88 vss vss 2410.80 -780.75 231 seg80 seg80 -1069.20 773.40 89 vl2 vl2 2487.00 -780.75 232 seg81 seg81 -1134.00 773.40 90 vl2 vl2 2568.30 -780.75 233 seg82 seg82 -1198.80 773.40 91 vl2 vl2 2649.60 -780.75 234 seg83 seg83 -1263.60 773.40 92 vl3 vl3 2730.90 -780.75 235 seg84 seg84 -1328.40 773.40 93 vl3 vl3 2812.20 -780.75 236 seg85 seg85 -1393.20 773.40 94 vl3 vl3 2893.50 -780.75 237 seg86 seg86 -1458.00 773.40 95 vl4 vl4 2974.80 -780.75 238 seg87 seg87 -1522.80 773.40 96 vl4 vl4 3056.10 -780.75 239 seg88 seg88 -1587.60 773.40 97 vl4 vl4 3137.40 -780.75 240 seg89 seg89 -1652.40 773.40 98 vl5 vl5 3218.70 -780.75 241 seg90 seg90 -1717.20 773.40 99 vl5 vl5 3300.00 -780.75 242 seg91 seg91 -1782.00 773.40 100 vl5 vl5 3381.30 -780.75 243 seg92 seg92 -1846.80 773.40 101 vl6 vl6 3462.60 -780.75 244 seg93 seg93 -1911.60 773.40 102 vl6 vl6 3543.90 -780.75 245 seg94 seg94 -1976.40 773.40 103 vl6 vl6 3625.20 -780.75 246 seg95 seg95 -2041.20 773.40 104 vr vr 3741.90 -780.75 247 seg96 seg96 -2106.00 773.40 105 vr vr 3818.10 -780.75 248 seg97 seg97 -2170.80 773.40 106 vss vss 3894.30 -780.75 249 seg98 seg98 -2235.60 773.40 107 cl cl 3970.50 -780.75 250 seg99 seg99 -2300.40 773.40 108 n/c com39 4114.80 -773.40 251 seg100 seg100 -2365.20 773.40 109 n/c com38 4179.60 -773.40 252 seg101 seg101 -2430.00 773.40 110 n/c com37 4244.40 -773.40 253 seg102 seg102 -2494.80 773.40 111 n/c com36 4309.20 -773.40 254 seg103 seg103 -2559.60 773.40 112 n/c com35 4374.00 -773.40 255 seg104 seg104 -2624.40 773.40 113 n/c com34 4438.80 -773.40 256 seg105 seg105 -2689.20 773.40 114 n/c com33 4503.60 -773.40 257 seg106 seg106 -2754.00 773.40 115 n/c com32 4568.40 -773.40 258 seg107 seg107 -2818.80 773.40 259 seg108 seg108 -2883.60 773.40 260 seg109 seg109 -2948.40 773.40 bump size : 261 seg110 seg110 -3013.20 773.40 pad 1~8, 108~115, 144~285 : 45x75um 262 seg111 seg111 -3078.00 773.40 pad 9~107 : 52.2x60um 263 seg112 seg112 -3142.80 773.40 pad 116~143, 286~313 : 75x45um 264 seg113 seg113 -3207.60 773.40 tolerance : +/- 3um 265 seg114 seg114 -3272.40 773.40 pad 1, 2, 3, ?.. -> 115 266 seg115 seg115 -3337.20 773.40 267 seg116 seg116 -3402.00 773.40 268 seg117 seg117 -3466.80 773.40 269 seg118 seg118 -3531.60 773.40 270 seg119 seg119 -3596.40 773.40 271 seg120 seg120 -3661.20 773.40 272 seg121 seg121 -3726.00 773.40 273 seg122 seg122 -3790.80 773.40 274 seg123 seg123 -3855.60 773.40 275 seg124 seg124 -3920.40 773.40 276 seg125 seg125 -3985.20 773.40 277 seg126 seg126 -4050.00 773.40 278 seg127 seg127 -4114.80 773.40 279 com32 com40 -4179.60 773.40 280 com33 com41 -4244.40 773.40 281 com34 com42 -4309.20 773.40 282 com35 com43 -4374.00 773.40 283 com36 com44 -4438.80 773.40 284 com37 com45 -4503.60 773.40 285 com38 com46 -4568.40 773.40 ssd1820a /21 x y
ssd1820a/21 10 rev 1.4 01/03 solomon res this pin is reset signal input. when the pin is low, initialization of the chip is executed. ps0 this pin use together with ps1 to determine the interface proto- col between the driver and mcu. refer to ps1 pin descriptions for more details. ps1 this pin use together with ps0 to determine the interface proto- col between the driver and mcu according to the following table. cs this pin is chip select input. the chip is enabled for display data/ command transfer only when cs is low. d/ c this input pin is to identify display data/command cycle. when the pin is high, the data written to the driver will be written into dis- play ram. when the pin is low, the data will be interpret as com- mand. this pin must be connected to v ss when 3-lines spi interface is used. r/ w ( wr ) this pin is microprocessor interface signal. when interfacing to an 6800-series microprocessor, the signal indicates read mode when high and write mode when low. when interfacing to an 8080- microprocessor, a data write operation is initiated when r/ w ( wr ) is low and the chip is selected. e( rd ) this pin is microprocessor interface signal. when interfacing to an 6800-series microprocessor, a data operation is initiated when e( rd ) is high and the chip is selected. when interfacing to an 8080-microprocessor, a data read operation is initiated when e( rd ) is low and the chip is selected. d 0 -d 7 these pins are 8-bit bi-directional data bus to be connected to the microprocessor?s data bus. when serial mode is selected, d 7 is the serial data input sda and d 6 is the serial clock input sck. intrs this pin is an input pin to enable the internal resistors network for the voltage regulator when intrs is high. when it is low, the exter- nal resistors r 1 /r 2 should be connected to v l6 , v r and v ss . ps0 ps1 interface l l 3-wire spi (write only) l h 4-wire spi (write only) h l 8080 parallel interface (read and write allowed) h h 6800 parallel interface (read and write allowed) ref this pin is an input pin to enable the internal reference voltage used for the internal regulator. when it is high, an internal refer- ence voltage source will be used. when it is low, an external refer- ence voltage source must be provided in v ext pin if internal regulator is used. v dd power supply pin. v ss ground. v ci reference voltage input for internal dc-dc converter. the volt- age of generated v cc equals to the multiple factor (2x, 3x, 4x, 5x or 6x) times v ci with respect to v ss . note: 1.) voltage at this input pin must be larger than or equal to v dd . 2.) 6x is avaliable for ssd1821 only. v cc this is the most positive voltage supply pin of the chip. it can be supplied externally or generated by the internal dc-dc converter. when using internal dc-dc converter as generator, voltage at this pin is for internal reference only. it cannot be used for driv- ing external circuitries. c 1p , c 2p , c 3p , c 4p , c 5p , c 1n and c 2n when internal dc-dc voltage converter is used, external capacitor(s) is/are connected among these pins. v l6 this pin is the most positive lcd driving voltage. it can be sup- plied externally or generated by the internal regulator. v r this pin is an input of the internal voltage regulator. when the internal resistors network for the voltage regulator is disabled (intrs is pulled low), external resistors should be connected between v ss and v r , and v r and v l6 , respectively (see applica- tion circuit). v ext this pin is an input to provide an external voltage reference for the internal voltage regulator when ref pin is pulled low. pin descriptions
solomon ssd1820a/21 11 rev 1.4 01/03 v l5 , v l4 , v l3 and v l2 lcd driving voltages. they can be supplied externally or gener- ated by the internal bias divider. they have the following relation- ship: v l6 > v l5 > v l4 > v l3 > v l2 > v ss for ssd1820a, a equals to 9 at por. for ssd1821, a equal to 10 at por. com0 - com63/com79 these pins provide the row driving signal com0 - com63/ com79 to the lcd panel. see table 1 or 2 about the com signal mapping in different multiplex ratio n. icons this pin is the special icons line com signal output. seg0 - seg127 these pins provide the lcd column driving signal. their voltage level is v ss during sleep mode and standby mode. cl this pin is the external clock input for the device which is enabled by using an extended command. under normal operation, this pin should be left opened and internal oscillator will be used after power on reset. n/c these no connection pins should not be connected to any sig- nal pins nor shorted together. they should be left open. 1:a bias v l5 (a-1)/a*v l6 v l4 (a-2)/a*v l6 v l3 2/a*v l6 v l2 1/a*v l6
ssd1820a/21 12 rev 1.4 01/03 solomon r/ w ( wr ) e( rd ) figure 4: display data read with the insertion of dummy read n n n+1 n+2 data bus write column address dummy read data read1 data read 2 data read 3 command decoder and command interface this module determines whether the input data is interpreted as data or command. data is directed to this module based upon the input of the d/ c pin. if d/ c is high, data is written to graphic display data ram (gddram). if d/ c is low, the input at d 0 -d 7 is interpreted as a command and it will be decoded and written to the corresponding command register. reset is of the same function as power on reset (por). once res receives a negative reset pulse of about 1us, all internal circuitry will be back to its initial status. refer to command description section for more information. mpu parallel 6800-series interface the parallel interface consists of 8 bi-directional data pins ( d 0 -d 7 ), r/ w ( wr ) , d/ c , e( rd ) and cs . r/ w ( wr ) input high indicates a read opera- tion from the graphic display data ram (gddram) or the status register. r/ w ( wr ) input low indicates a write operation to display data ram or internal command registers depending on the status of d/ c input. the e( rd ) and cs input serves as data latch signal (clock) when they are high and low respectively. refer to figure 1 of parallel timing characteristics for parallel interface timing diagram of 6800-series microprocessors. in order to match the operating frequency of display ram with that of the microprocessor, some pipeline processing is internally performed which requires the insertion of a dummy read before the first actual display data read. this is shown in figure 4 below. mpu parallel 8080-series interface the parallel interface consists of 8 bi-directional data pins ( d 0 -d 7 ), r/ w ( wr ), e( rd ) , d/ c and cs . the cs input serves as data latch signal (clock) when it is low. whether it is display data or status register read is controlled by d/ c . r/ w ( wr ) and e( rd ) input indicates a write or read cycle when cs is low. refer to figure 2 of parallel timing characteristics for parallel interface timing diagram of 8080-series microprocessor. similar to 6800-series interface, a dummy read is also required before the first actual display data read. operation of liquid crystal display driver description of block diagram module mpu serial 4-wire interface the serial interface consists of serial clock sck, serial data sda, d/ c and cs . sda is shifted into a 8-bit shift register on every rising edge of scl in the order of d 7 , d 6 ,... d 0 . d/ c is sampled on every eighth clock and the data byte in the shift register is written to the display data ram or command register in the same clock. no extra clock or com- mand is required to end the transmission. mpu serial 3-wire interface operation is similar to 4-wire serial interface while d/ c is not been used. the display data length instruction is used to indicate that a specified number display data byte (1-256) are to be transmitted. next byte after the display data string is handled as a command. it should be noted that if there is a signal glitch at sck that causing an out of synchronization in the serial communication, a hardware reset pulse at res pin is required to initialize the chip for re-synchronization. modes of operation 6800 parallel 8080 parallel serial data read yes yes no data write yes yes yes command read status only status only no command write yes yes yes segment and common outputs are provided. for vertical scrolling of display, an internal register storing the display start line can be set to control the portion of the ram data to be mapped to the display. figure 5, 6 show the case in which the display start line register is set at 38h. graphic display data ram (gddram) the gddram is a bit mapped static ram holding the bit pattern to be displayed. the size of the ram is 128 x 65 = 8320bits for ssd1820a; 128 x 81 = 10368bits for ssd1821. figure 5, 6 are the description of the gddram address map. for mechanical flexibility, re-mapping on both
solomon ssd1820a/21 13 rev 1.4 01/03 page 7 page 6 page 5 page 4 page 3 page 2 page 1 page 0 lsb msb lsb msb lsb msb msb lsb msb lsb msb lsb msb lsb msb [d7] lsb [d0] 3 8 h com0 (com 63 ) com7 (com 56 ) icons com 63 (com0) com 8 (com 55 ) seg 0 seg 127 the configuration in parentheses represent the remapping of rows and columns note: figure 5. ssd1820a graphic display data ram (gddram) address map (with vertical scroll value 38h) column address 00h column address 7f h page 8 (lsb) com scan mode normal (remapped) (00h) (7fh) segment remap enabled
ssd1820a/21 14 rev 1.4 01/03 solomon page 7 page 6 page 5 page 4 page 3 page 2 page 1 page 0 lsb msb lsb msb lsb msb msb lsb msb lsb msb lsb msb lsb msb [d7] lsb [d0] 3 8 h com0 (com 79 ) com 23 (com 56 ) icons com 79 (com0) com 24 (com 55 ) seg 0 seg 127 the configuration in parentheses represent the remapping of rows and columns note: figure 6. ssd1821 graphic display data ram (gddram) address map (with vertical scroll value 38h) column address 00h column address 7f h page 10 com scan mode normal (remapped) (00h) (7fh) segment remap enabled page 9 page 8 msb lsb msb lsb (lsb)
solomon ssd1820a/21 15 rev 1.4 01/03 figure 7. oscillator circuitry lcd driving voltage generator and regulator this module generates the lcd voltage needed for display output. it takes a single supply input and generate necessary bias voltages. it consists of: 1. 2 x, 3 x , 4 x , 5x and 6x dc-dc voltage converter please refer to application notes. please note that ssd1820a works up to 5x and ssd1820at works up to 4x only. 2. voltage regulator feedback gain control for initial lcd voltage. external resistors are connected between v ss and v r , and between v r and vl6. these resistors are chosen to give the desired vl6 according to the following equation: where v ref is the internally generated reference voltage with a known r 1 and r 2 . typical value for v ref is 2.1v r 1 is the resistance of the resistor between v ss and v r . r 2 is the resistance of the resistors between v r and v l6 . a is the software contrast level from 0 to 63. g = 1 if intrs = vdd; ref = vdd g = 0.84 if intrs = vss; ref = vdd 3. bias divider if the output op-amp buffer option in set power control register command is enabled, this circuit block will divide the regulator output (v l6 ) to give the lcd driving levels (v l2 - v l5 ). a low power consumption circuit design in this bias divider saves most of the display current comparing to traditional design. stablizing capacitors (0.47~2uf) are required to be connected between these voltage level pins (v l2 - v l5 ) and v ss . if the lcd panel loading is heavy, capacitors and four additional resistors are suggest- ref con v v - - = ) 210 63 1 ( a con l v r r v + = ) 1 ( 1 2 6 g ref con v v - - = ) 210 63 1 ( a con l v r r v + = ) 1 ( 1 2 6 g ed to add to the application circuit as follows: connections for heavy loading applications 4. contrast control software control of 64 voltage levels of lcd voltage. 5. bias ratio selection circuitry software control of 1/ 4 to 1/ 10 bias ratio to match the characteris- tic of lcd panel. note: ssd1820a has 1/4 to 1/9 bias only. 6. self adjust temperature compensation circuitry provide 2 different compensation grade selections to satisfy the various liquid crystal temperature grades. the grading can be selected by software control. defaulted temperature coefficient (tc) value is -0. 05 %/ o c for ssd1820a and -0.07%/ o c for ssd1821 . 193/209 bit latch a register carries the display signal information. in 1 28 x 65/81 dis- plamod e . data will be fed to the hv-buffer cell and level-shifted to the required level. level selector level selector is a control of the display synchronization. display voltage can be separated into two sets and used with different cycles. synchronization is important since it selects the required lcd voltage level to the hv buffer cell, which in turn outputs the com or seg lcd waveform. ssd1820a/21 series remarks: 1. c2 = 0.47 ~ 2.0uf 2. rl = 100k ~ 1m v ss v l2 v l3 v l4 v l5 v l6 rl rl rl rl + v ss c2 + c2 + c2 + c2 + c2 oscillator circuit this module is an on-c hip low power rc oscillator circuitry (figure 7 ). the oscillator generates the clock for the dc-dc voltage converter. this clock is also used in the display timing generator. oscillation circuit enable osc1 osc2 internal pwell resistor oscillator enable buffer enable (cl)
ssd1820a/21 16 rev 1.4 01/03 solomon hv buffer cell (level shifter) hv buffer cell works as a level shifter which translates the low voltage output signal to the required driving voltage. the output is shifted out with an internal frm clock which comes from the display timing generator. the voltage levels are given by the level selector which is synchronized with the internal m signal. reset circuit when res input is low, the chip is initialized to the following: 1. page address is set to 0 2. column address is set to 0 3. display is off 4. display start line is set to 0 (gddram page 0, d0) 5. display offset is set to 0 (com0 is mapped to row0) 6. 128x64 for ssd1820a / 128x80 for ssd1821 7. normal/reverse display is normal 8. n-line inversion register is 0 9. entire display is off 10. power control register (vc, vr, vf) is set to (0,0,0) 11. 2x/3x booster is selected 12. internal resistor ratio register is set to 0h 13. software contrast is set to 32 14. lcd bias ratio is set to 1/9 for ssd1820a and 1/10 for ssd1821. 15. normal scan direction of com outputs 16. segment remap is disabled (seg0 display column address 0) 17. internal oscillator is off 18. test mode is off 19. temperature coefficient is set to ptc0 for ssd1820a and ptc1 for ssd1821. 20. icon display line is off 21. interface lock / unlock register will be clear when reset command is issued, the following parameters are initialized only: 1. page address is set to 0 2. column address is set to 0 3. initial display line is set to 0 (point to display ram page 0, d0) 4. internal resistor ratio register is set to 0h
solomon ssd1820a/21 17 rev 1.4 01/03 time slot com0 com1 seg0 seg1 m * note : n is the number of multiplex ratio including icon line if it is enabled, n is equal to 64/80 on por. v l6 v l 5 v l 4 v l 3 v l 2 v ss v l6 v l 5 v l 4 v l 3 v l 2 v ss v l6 v l 5 v l 4 v l 3 v l 2 v ss v l6 v l 5 v l 4 v l 3 v l 2 v ss 1 2 3 4 5 6 7 8 9 . . . n * 1 2 3 4 5 6 7 8 9 . . . n * 1 2 3 4 5 6 7 8 9 . . . n * 1 2 3 4 5 6 7 8 9 . . . n * figure 8a. lcd display example ?0? lcd panel driving waveform the following is an example of how the common and segment drivers may be connected to a lcd panel. the waveforms shown in figure 8a and 7 b illustrate the desired multiplex scheme with n-line inversion feature is disabled (default). figure 8b. lcd driving signal from ssd1820a/ssd1821 com1 com2 com3 com4 com5 com6 com7 s e g 1 s e g 2 s e g 3 s e g 4 com0 s e g 0
ssd1820a/21 18 rev 1.4 01/03 solomon command table hex d7 d6 d5 d4 d3 d2 d1 d0 command comment 00~0f 0 0 0 0 c3 c2 c1 c0 set lower column address sets the lower nibble of the column address pointer for ram access. the pointer is reset to 0 after reset. 10~17 0 0 0 1 0 c6 c5 c4 set upper column address sets the upper nibble of the column address pointer for ram access. the pointer is reset to 0 after reset. 18~1f reserved reserved 20~27 0 0 1 0 0 r2 r1 r0 set internal regulator resis- tor ratio the internal regulator gain (1+r2/r1)vcon increases as r2r1r0 is increased from 000b to 111b. the resistor ratio (1+r2/r1) is given by: r2r1r0 = 000: 2.3 (por) r2r1r0 = 001: 3.0 r2r1r0 = 010: 3.7 r2r1r0 = 011: 4.4 r2r1r0 = 100: 5.1 r2r1r0 = 101: 5.8 r2r1r0 = 110: 6.5 r2r1r0 = 111: 7.2 28~2f 0 0 1 0 1 vc vr vf set power control register vc=0: turns off the internal voltage booster (por) vc=1: turns on the internal voltage booster vr=0: turns off the internal regulator (por) vr=1: turns on the internal regulator vf=0: turns off the output op-amp buffer (por) vf=1: turns on the output op-amp buffer 30~3f reserved reserved 40~43 0 x 1 l6 0 l5 0 l4 0 l3 0 l2 x l1 x l0 set display start line the next command specifies the row address pointer (0-63) of the ram data to be displayed in com0. this command has no effect on coms. the pointer is set to 0 after reset. 44~47 0 x 1 c6 0 c5 0 c4 0 c3 1 c2 x c1 x c0 set display offset the next command specifies the mapping of first display line (com0) to one of row0~63. this command has no effect on coms. com0 is mapped to row0 after reset. 48~4b 0 x 1 d6 0 d5 0 d4 1 d3 0 d2 x d1 x d0 set multiplex ratio the next command specifies the number of lines, excluding coms, to be displayed. with icon is disabled (por), duties 1/16~1/64 or 1/80 could be selected. with icon enabled, the available duty ratios are 1/17~ 1/65 or 1/81. 4c~4f 0 x 1 x 0 x 0 n4 1 n3 1 n2 x n1 x n0 set n-line inversion the next command sets the n-line inversion register from 3 to 33 lines to reduce display crosstalk. register values from 00001b to 11111b are mapped to 3 lines to 33 lines respectively. value 00000b disables the n-line inversion, which is the por value. to avoid a fix polarity at some lines, it should be noted that the total number of mux (including the icon line) should not be a multiple of the lines of inversion (n). 50~57 0 1 0 1 0 b2 b1 b0 set lcd bias sets the lcd bias from 1/4 ~ 1/10 according to b2b1b0: 000: 1/4 bias 001: 1/5 bias 010: 1/6 bias 011: 1/7bias 100: 1/8 bias 101: 1/9 bias (por for ssd1820a) 110: 1/9 bias (for ssd1820a) 1/10 bias (por for ssd1821) 111: 1/9 bias (for ssd1820a); 1/10 bias (for ssd1821)
solomon ssd1820a/21 19 rev 1.4 01/03 58~63 reserved reserved 64~67 0 1 1 0 0 1 b1 b0 set dc-dc conveter factor sets the dc-dc multiplying factor from 2x to 6x b1b0: 00: 2x/3x (por, 2x or 3x multiplying depended on the dc-dc conveter configuration) 01: 4x 10: 5x (for ssd1820a) 11: 5x (for ssd1820a); 6x (for ssd1821) 68~80 reserved reserved 81 1 x 0 x 0 c5 0 c4 0 c3 0 c2 0 c1 1 c0 set contrast control regis- ter the next command sets one of the 64 contrast levels. the darkness increase as the contrast level increase. the level is set to 32 after por. 82~9f reserved reserved a0~a1 1 0 1 0 0 0 0 s0 set segment re-map s0=0: column address 00h is mapped to seg0 (por) s0=1: column address 7fh is mapped to seg0 a2~a3 1 0 1 0 0 0 1 c0 set icon enable c0=0: disable icon row (mux = 16 to 64/80, por) c0=1: enable icon row (mux = 17 to 65/81) a4~a5 1 0 1 0 0 1 0 e0 set entire display on/off e0=0: normal display (dispaly according to ram con- tents, por) e0=1: all pixels are on regardless of the ram contents *note: this command will override the effect of ?set normal/reverse display? a6~a7 1 0 1 0 0 1 1 r0 set normal/reverse display r0=0: normal display (dispaly according to ram con- tents, por) r0=1: reverse display (on and off pixels are inverted) *note: this command will not affect the display of the icon lines a8 reserved reserved a9 1 0 1 0 1 0 0 1 set power save mode enter sleep mode aa reserved reserved ab 1 0 1 0 1 0 1 1 start internal oscillator oscillator is off after reset, until this command is issued. this command is required even if external oscil- lator is used. ae~af 1 0 1 0 1 1 1 d0 set display on/off d0=0: display off (por) d0=1: display on b0~bf 1 0 1 1 p3 p2 p1 p0 set page address set gddram page address (0~10) using p3p2p1p0 for ram access. the page address is sets to 0 after reset. c0~cf 1 1 0 0 s0 x x x set com output scan direction s0=0: normal mode (por) s0=1: remapped mode. com0 to com[n-1] becomes com[n-1] to com0 when the duty is set to n. see figure 5/6 as an example for n equals to 64/80. *note: this command will not affect the display of the icon lines d0~e0 reserved reserved e1 1 1 1 0 0 0 0 1 exit power-save mode dc-dc converter, regulator and divider status before entering the power-save mode is restored. at por, power-save mode is released. e2 1 1 1 0 0 0 1 0 software reset initialize some internal registers e3 reserved reserved e4 1 1 1 0 0 1 0 0 exit n-line inversion the frame will be inverted once per frame e5~e7 reserved reserved
ssd1820a/21 20 rev 1.4 01/03 solomon extended command table read status byte a 8 bits status byte will be placed to the data bus if a read operation is performed if d/ c is low. the status byte is defined as follow. data read / write to read data from the gddram, input high to r/ w ( wr ) pin and d/ c pin for 6800-series parallel mode, low to e( rd ) pin and high to d/ c pin for 8080-series parallel mode. no data read is provided for serial mode. in normal mode, gddram column address pointer will be increased by one automatically after each data read. also, a dummy read is required before the first data is read. see figure 4 in func- e8 1 d7 1 d6 1 d5 0 d4 1 d3 0 d2 0 d1 0 d0 set display data length this command is valid only at 3-wire spi (ps0=ps1=l) the next command specifies the number of bytes of dis- play data to be written after this composite command. d(7:0)=00: 1 byte of display data is to be sent d(7:0)=ff: 256 bytes of display data is to be sent e9~ef reserved reserved f0~ff 1 1 1 1 x x x x extended features test mode commands and extended features, see extended command table. bit pattern command comment 11110001 00001x 2 x 1 x 0 x 2 x 1 x 0 : set tc value x 2 x 1 x 0 = 000: -0.05%/c (por for 1820a) x 2 x 1 x 0 = 001: -0.07%/c (por for 1821) 11110010 0010x 3 x 2 x 1 x 0 x 3 : select oscillator source x 2 x 1 x 0 : set oscillator value x 3 = 0: internal rc oscillator is selected (por) x 3 = 1: external oscillator from cl pin is selected if x 3 = 0, x 2 x 1 x 0 = 000: -16% x 2 x 1 x 0 = 001: -10% x 2 x 1 x 0 = 010: 0% (por) x 2 x 1 x 0 = 011: +10% x 2 x 1 x 0 = 100: +16% x 2 x 1 x 0 = 101: +30% x 2 x 1 x 0 = 110: +54% x 2 x 1 x 0 = 111: +81% 11111101 00010l10 l : interface lock / unlock l = 0 interface unlock (por) l = 1 interface lock other than above reserved d7 d6 d5 d4 d3 d2 d1 d0 comment busy on res 0 1 0 0 ds0 busy=0: chip is idle busy=1: chip is executing instruction on=0: display is off on=1: dispaly is on res=0: chip is idlex res=1: chip is executing reset ds0=0: ssd1820a; ds0=1:ssd1821
solomon ssd1820a/21 21 rev 1.4 01/03 tional description. to write data to the gddram, input low to r/ w ( wr ) pin and high to d/ c pin for 6800-series parallel mode. for serial interface, it will always be in write mode. gddram column address pointer will be increased by one automatically after each data write. the address will be reset to 0 in next data read/write operation is executed when it is 127. address increment table (automatic) address increment is done automatically after data read/write. the column address pointer of gddram is also affected. it will be reset to 0 in next data read/write operation is executed when it is 127. commands required for r/ w ( wr ) actions on ram * no need to resend the command again if it is set previously. the read / write action to the display data ram does not depend on the display mode. this means the user can change the ram cont ent whether the target ram content is being displayed or not. d/ c r/ w ( wr ) comment address increment 0 0 write command no 0 1 read status no 1 0 write data yes 1 1 read data yes r/ w ( wr ) actions on rams commands required read/write data from/to gddram. set gddram page address set gddram column address read/write data (1011x 3 x 2 x 1 x 0 )* (0001x 3 x 2 x 1 x 0 )* (0000x 3 x 2 x 1 x 0 )* (x 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 )
ssd1820a/21 22 rev 1.4 01/03 solomon command description set display on/off this command turns the display on/off, by the value of the lsb. set display start line this command is to set display start line register to deter- mine starting address of display ram to be displayed by select- ing a value from 0 to 63/79. with value equals to 0, d0 of page 0 is mapped to com0. with value equals to 1, d1 of page0 is mapped to com0. the display start line values of 0 to 63/79 are assigned to page 0 to 7/9. set page address this command positions the page address to 0 to 8/10 possi- ble positions in gddram. refer to figure 5/6. set higher column address this command specifies the higher nibble of the 7-bit column address of the display data ram. the column address will be incremented by each data access after it is pre-set by the mcu and returning to 0 once overflow (>127). set lower column address this command specifies the lower nibble of the 7-bit column address of the display data ram. the column address will be incremented by each data access after it is pre-set by the mcu and returning to 0 once overflow (>127). set segment re-map this commands changes the mapping between the display data column address and segment driver. it allows flexibility in layout during lcd module assembly. refer to figure 5/6. set normal/reverse display this command sets the display to be either normal/reverse. in normal display, a ram data of 1 indicates an ?on? pixel while in reverse display, a ram data of 0 indicates an ?on? pixel. the icon line is not affected by this command. set entire display on/off this command forces the entire display, including the icon row, to be ?on? regardless of the contents of the display data ram. this command has priority over normal/reverse dis- play. to executed this command, set display on command must be sent in advance. set lcd bias this command selects a suitable bias ratio (1/4 to 1/9 or 1/10) required for driving the particular lcd panel in use. the por default for ssd1820a is set to 1/9 bias; and 1/10 bias for ssd1821. software reset this command causes some of the internal status of the chip to be initialized: 1. page address is set to 0 2. column address is set to 0 3. initial display line is set to 0 (point to display ram page 0, d0) 4. internal resistor ratio register is set to (0,0,0) 5. software contrast is set to 32 set com output scan direction this command sets the scan direction of the com output allowing layout flexibility in lcd module assembly. set power control register this command turns on/off the various power circuits asso- ciated with the chip. set internal regulator resistors ratio this command is to enable any one of the eight internal resis- tor (irs) settings for different regulator gains when using internal regulator resistor network (intrs pin pulled high). when external resistors are used, intrs must be connected to vss. the contrast control voltage range curves is given in the figure below: 0.0 16.0 8.0 4.0 12.0 10.0 6.0 14.0 2.0 vl6 voltage (v) 0 63 31 15 47 7 23 39 55 irs setting 111 110 101 100 011 010 001 000 contrast control setting default tc
solomon ssd1820a/21 23 rev 1.4 01/03 set contrast control register this command adjusts the contrast of the lcd panel by changing vl6 of the lcd drive voltage provided by the on-chip power circuits. vl6 is set with 64 steps (6-bit) contrast control register. it is a compound commands: set display offset the next command specifies the mapping of display start line (com0 if display start line register equals to 0) to one of row0- 63/79. this command has no effect on coms. com0 is mapped to row0 after reset. set multiplex ratio this command switches default 64 multiplex mode to any mul- tiplex from 16 to 64/80, if icon is disabled (por). when icon is set enable, the corresponding multiplex ratio setting will be mapped to 17 to 65/81. the chip pads row0-row63/row79 will be switched to corresponding com signal output as specified in ta- ble 1 or 2. set power save mode to force the chip to enter sleep mode. exit power save mode this command releases the chip from sleep mode and return to normal operation. set n-line inversion number of line inversion is set by this command for reducing crosstalk noise. 3 to 33-line inversion operations could be selected. at por, this operation is disabled. it should be noted that the total number of mux (including the icon line) should not be a multiple of the inversion number (n). or else, some lines will not change their polarity during frame change. exit n-line inverstion this command releases the chip from n-line inversion mode. the driving waveform will be inverted once per frame after issu- ing this command. set dc-dc converter factor internal dc-dc converter factor is set by this command. for ssd1820a, 2x to 5x multiplying factors could be selected. for ssd1821, 2x to 6x mutiplying factors could be selected. 2x/3x, 4x, 5x and 6x factors are selected uising this command. hard- ware configuration is used for 2x or 3x setup. set icon enable set contrast control register contrast level data changes complete? no yes this command enable/disable the icon display. start internaloscillator after por, the internal oscillator is off. it should be turned on by sending this command to the chip. set display data length this two-byte command only valid when 3-wire spi config- uration is set by h/w input (ps0=ps1=l). the second 8-bit is used to indicate that a specified number display data byte (1- 256) are to be transmitted. next byte after the display data string is handled as a command. set test mode this command force the driver chip into its test mode for internal testing of the chip. under normal operation, user should not use this command. status register read this command is issued by setting d/ c low during a data read (refer to figure 1 and 2 parallel interface waveform). it al- lows the mcu to monitor the internal status of the chip. no sta- tus read is provided for serial mode. extended commands these commands are used, in addition to basic commands, to enable the enhanced features designed in the chips. set temperature coefficient (tc) value this command is to set 1 out of 2 different temperature coefficients in order to match various liquid crystal tempera- ture grades. enable external oscillator input. this command enables the external clock input from cl pin. select oscillator source this command is used to adjust the oscillator frequency to desire frame frequency. set interface lock / unlock after the interface lock command is issued, no more data or commands will be accepted until an interface unlock com- mand is issued.
ssd1820a/21 24 rev 1.4 01/03 solomon maximum ratings* (voltages referenced to v ss ) symbol parameter value unit v dd supply voltage -0.3 to +4.0 v v cc v ss -0.3 to v ss +15.0 v v ci booster supply voltage v dd to +4.0 v v in input voltage v ss -0.3 to v dd +0.3 v i current drain per pin excluding v dd and v ss 25 ma t a operating temperature -40 to +85 c t stg storage temperature range -65 to +150 c * maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the limits in the electrical characteristics tables or pin descrip- tion section. this device contains circuitry to protect the inputs against damage due to high static voltages or elec- tric fields; however, it is advised that normal precau- tions to be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. for proper operation it is recom- mended that v in and v out be constrained to the range v ss < or = (v in or v out ) < or = v dd . reliability of operation is enhanced if unused input are con- nected to an appropriate logic voltage level (e.g., either v ss or v dd ). unused outputs must be left open. this device may be light sensitive. caution should be taken to avoid exposure of this device to any light source during normal operation. this device is not radiation protected. electrical characteristics (voltage referenced to v ss , v dd =1.8 to 3.3v, t a =-40 to 85c; unless otherwise specified.) symbol parameter test condition min typ (at 25 c) max unit v dd logic circuit supply voltage range voltage generator circuit supply voltage range (absolute value referenced to v ss ) 1.8 2.7 3.3 v i ac i dp1 i dp2 i sb i sleep access mode supply current drain (v dd pins display mode supply current drain (v dd pins) display mode supply current drain (v dd pins) standby mode supply current drain (v dd pins) sleep mode supply current drain (v dd pins) v dd = 2.7v, voltage generator on, 4x converter enabled, write accessing, t cyc =3.3mhz, osc. freq.=31khz, display on. v dd = 2.7v, v cc = 10.8v, voltage generator off, external divider enabled. read/write halt, osc. freq. = 31khz, display on, vl6 = 9.0v. v dd = v ci = 2.7v, v cc = 10.8v, voltage generator on, 4x dc-dc converter enabled, v ci pin con- nected to v dd . internal divider enabled. read/write halt, osc. freq. = 31khz, display on, vl6 = 9.0v. v dd =2.7v, lcd driving waveform off, osc. freq. = 31khz, read/write halt. v dd = 2.7v, lcd driving waveform off, oscillator off, read/write halt. - - - - - 300 15 90 8.0 0.5 600 26 120 37 3 m a m a m a m a m a v cc v lcd lcd driving voltage generator output (v cc pin) dc-dc converter efficiency lcd driving voltage input (v cc pin) display on, voltage generator enabled, dc/dc converter enabled, osc. freq.=31khz, regulator enabled, divider enabled. i cc < 20ua voltage generator disabled. v dd 95 4.0 - 99 - 15.0 15.0 v % v v ref external reference voltage input internal reference voltage internal reference voltage source disable (ref pin pulled low), external reference voltage input to v ext pin. internal reference voltage source enabled (ref pin pulled high), v ext pin nc. 2.04 2.10 2.10 2.16 v v
solomon ssd1820a/21 25 rev 1.4 01/03 * the formula for the temperature coefficient is: v oh1 v ol1 vl6 vl6 output high voltage (d 0 -d 7 ) output low voltage (d 0 -d 7 ) lcd driving voltage source (vl6 pin) lcd driving voltage source (vl6 pin) i out = +500 m a i out = -500 m a regulator enabled (vl6 voltage depends on int/ext contrast control) regulator disable 0.8*v d d 0 v dd - - - - floating v dd 0.2*v d d v cc - 0.5 - v v v v v ih1 v il1 input high voltage ( res , ps0, ps1, cs , d/ c , r/ w , d 0 -d 7 , ref, intrs) input low voltage ( res , ps0, ps1, cs , d/ c , r/ w , d 0 -d 7 , ref, intrs) 0.8*v d d 0 - - v dd 0.2*v d d v v v l6 v l5 v l4 v l3 v l2 v l6 v l5 v l4 v l3 v l2 lcd display voltage output (v l6 , v l5 , v l4 , v l3 , v l2 pins)\ lcd display voltage inpu (v l6 , v l5 , v l4 , v l3 , v l2 pins) bias divider enabled, 1:a bias ratio voltage reference to v ss , external voltage genera- tor, bias divider disabled - - - - - v l5 v l4 v l3 v l2 v ss v l6 (a-1)/a*v l6 (a-2)/a*v l6 2/a*v l6 1/a*v l6 - - - - - - - - - - v cc v l6 v l5 v l4 v l3 v v v v v v v v v v i oh i ol i oz output high current source (d 0 -d 7 ) output low current drain (d 0 -d 7 ) output tri-state current drain source (d 0 -d 7 ) v out =v dd -0.4v v out =0.4v 50 - -1 - - - - -50 1 m a m a m a i il /i ih input current ( res , ps0, ps1, cs , e, d/ c , r/ w , d 0 -d 7 , ref, intrs) -1 - 1 m a c in input capacitance (all logic pins) - 5 7.5 pf d vl6 variation of vl6 output (1.8v < v dd < 3.0v) regulator enabled, internal contrast control enabled, set contrast control register = 0 - 2 - % ptc0 ptc1 temperature coefficient compensation* temperature coefficient 0 temperature coefficient 1 voltage regulator enabled (por for ssd1820a) voltage regulator enabled (por for ssd1821) -0.04 -0.06 -0.05 -0.07 -0.06 -0.08 % % tc(%)= v l6 at 50c - v l6 at 0c 50c - 0c x 1 v l6 at 25c x 100%
ssd1820a/21 26 rev 1.4 01/03 solomon ac electrical characteristics (t a =25c, voltage referenced to v ss , v dd =v ci =2.7v, unless otherwise specified.) symbol parameter test condition min typ (at 25 c) max unit f osc oscillation frequency of display timing generator (ssd1820a/21) internal oscillator enabled 28.4 33 39 khz f frm frame frequency (ssd1820a) display on, set 128 x 64 graphic display mode, icon line enabled. por oscillator settings 70 84.6 100 hz frame frequency (ssd1821) display on, set 128 x 80 graphic display mode, icon line enabled. por oscillator settings 70 81.5 100 hz f osc 6 x 65 f osc 5 x 81
solomon ssd1820a/21 27 rev 1.4 01/03 table 3a. parallel timing characteristics (t a =-40 to 85c, v dd =2.7v, v ss =0v) symbol parameter min typ max unit t cycle clock cycle time (write cycle) 66 - - ns t as address setup time 0 - - ns t ah address hold time 0 - - ns t dsw write data setup time 10 - - ns t dhw write data hold time 2 - - ns t dhr read data hold time 10 - - ns t oh output disable time - - 30 ns t acc access time (ram) access time (command) - - - - 80 25 ns ns pw csl chip select low pulse width (read ram) chip select low pulse width (read command) chip select low pulse width (write) 95 40 15 - - - - ns ns pw csh chip select high pulse width (read) chip select high pulse width (write) 30 30 - - - - ns ns t r rise time - - 10 ns t f fall time - - 10 ns valid data t cycle t dsw t as t ah t dhr t acc cs d/ c d 0 -d 7 e valid data d 0 -d 7 (write data to driver) (read data from driver) t dhw pw csl pw csh t f t r r/ w t oh figure 1a. parallel 6800-series interface timing characteristics (ps0 = h, ps1 = h)
ssd1820a/21 28 rev 1.4 01/03 solomon table 3b. parallel timing characteristics (t a =-40 to 85c, v dd =1.8v, v ss =0v) symbol parameter min typ max unit t cycle clock cycle time (write cycle) 80 - - ns t as address setup time 0 - - ns t ah address hold time 0 - - ns t dsw write data setup time 15 - - ns t dhw write data hold time 5 - - ns t dhr read data hold time 15 - - ns t oh output disable time - - 40 ns t acc access time (ram) access time (command) - - - - 100 35 ns ns pw csl chip select low pulse width (read ram) chip select low pulse width (read command) chip select low pulse width (write) 120 55 20 - - - - - - ns ns ns pw csh chip select high pulse width (read) chip select high pulse width (write) 40 40 - - - - ns ns t r rise time - - 10 ns t f fall time - - 10 ns valid data t cycle t dsw t as t ah t dhr t acc cs d/ c d 0 -d 7 e valid data d 0 -d 7 (write data to driver) (read data from driver) t dhw pw csl pw csh t f t r r/ w t oh figure 1b. parallel 6800-series interface timing characteristics (ps0 = h, ps1 = h)
solomon ssd1820a/21 29 rev 1.4 01/03 table 4a. parallel timing characteristics (t a =-40 to 85c, v dd =2.7v, v ss =0v) symbol parameter min typ max unit t cycle clock cycle time (write cycle) 66 - - ns t as address setup time 0 - - ns t ah address hold time 0 - - ns t dsw write data setup time 10 - - ns t dhw write data hold time 2 - - ns t dhr read data hold time 10 - - ns t oh output disable time - - 30 ns t acc access time (ram) access time (command) - - - - 80 25 ns ns pw csl chip select low pulse width (read ram) chip select low pulse width (read command) chip select low pulse width (write) 95 40 15 - - - - ns ns pw csh chip select high pulse width (read) chip select high pulse width (write) 30 30 - - - - ns ns t r rise time - - 10 ns t f fall time - - 10 ns figure 2a. parallel 8080-series interface timing characteristics (ps0 = h, ps1 = l) valid data t cycle t dsw t as t ah t dhr t acc cs d/ c d 0 -d 7 rd (e) valid data d 0 -d 7 (write data to driver) (read data from driver) t dhw pw csl pw csh t f t r t oh wr (r/ w )
ssd1820a/21 30 rev 1.4 01/03 solomon table 4b. parallel timing characteristics (t a =-40 to 85c, v dd =1.8v, v ss =0v) symbol parameter min typ max unit t cycle clock cycle time (write cycle) 80 - - ns t as address setup time 0 - - ns t ah address hold time 0 - - ns t dsw write data setup time 15 - - ns t dhw write data hold time 5 - - ns t dhr read data hold time 15 - - ns t oh output disable time - - 40 ns t acc access time (ram) access time (command) - - - - 100 35 ns ns pw csl chip select low pulse width (read ram) chip select low pulse width (read command) chip select low pulse width (write) 120 55 20 - - - - - - ns ns ns pw csh chip select high pulse width (read) chip select high pulse width (write) 40 40 - - - - ns ns t r rise time - - 10 ns t f fall time - - 10 ns valid data t cycle t dsw t as t ah t dhr t acc cs d/ c d 0 -d 7 rd (e) valid data d 0 -d 7 (write data to driver) (read data from driver) t dhw pw csl pw csh t f t r t oh wr (r/ w ) figure 2b. parallel 8080-series interface timing characteristics (ps0 = h, ps1 = l)
solomon ssd1820a/21 31 rev 1.4 01/03 table 5a. serial timing characteristics (t a =-40 to 85c, v dd =2.7v, v ss =0v) symbol parameter min typ max unit t cycle clock cycle time 59 - - ns t as address setup time 10 - - ns t ah address hold time 5 - - ns t css chip select setup time 10 - - ns t csh chip select hold time 5 - - ns t dsw write data setup time 10 - - ns t dhw write data hold time 10 - - ns t clkl clock low time 10 - - ns t clkh clock high time 20 - - ns t r rise time - - 10 ns t f fall time - - 10 ns figure 3a. serial timing characteristics (ps0 = l) valid data t cycle t dsw t as t ah sck d/ c sda cs t dhw t clkl t clkh t f t r t css t csh (required if ps1 = h) d7 d6 d5 d4 d3 d2 d1 d0 sck sda cs
ssd1820a/21 32 rev 1.4 01/03 solomon table 5b. serial timing characteristics (t a =-40 to 85c, v dd =1.8v, v ss =0v) symbol parameter min typ max unit t cycle clock cycle time 70 - - ns t as address setup time 15 - - ns t ah address hold time 10 - - ns t css chip select setup time 15 - - ns t csh chip select hold time 10 - - ns t dsw write data setup time 15 - - ns t dhw write data hold time 15 - - ns t clkl clock low time 15 - - ns t clkh clock high time 30 - - ns t r rise time - - 10 ns t f fall time - - 10 ns figure 3b. serial timing characteristics (ps0 = l) valid data t cycle t dsw t as t ah sck d/ c sda cs t dhw t clkl t clkh t f t r t css t csh (required if ps1 = h) d7 d6 d5 d4 d3 d2 d1 d0 sck sda cs
solomon ssd1820a/21 33 rev 1.4 01/03 ssd1821 die (die face up) seg0 -------------------------------- seg127 display panel size 128 x 80 + 2 icon lines 80 mux segment remapped [command: a1] d 0 - d 7 r / w c s r e s d / c v s s v c c i n t r s external vcc=10.8v remapped com scan direction [command: c8] application circuit: bias divider enabled with external v cc . vl2 vl3 vl4 vl5 vdd=2.7v optional for external resistors gain control [intrs pulled to vss] 0.47 m f - 2.0 m f r1 r2 vl6 vr vss r e f nc com6 com7 : : : com20 com19 : : : com30 com31 nc c o m 4 6 c o m 4 5 c o m 4 4 c o m 4 3 c o m 4 2 c o m 4 1 c o m 4 0 s e g 1 2 7 s e g 1 2 6 : : : : : : : : : : : : s e g 6 4 s e g 6 3 : : : : : : : : : : : : : : : : : : s e g 2 s e g 1 s e g 0 i c o n s c o m 0 c o m 1 c o m 2 c o m 3 c o m 4 c o m 5 nc com47 com48 : : : com52 com53 : : : com71 com72 nc remapped com scan direction [command: c8] com40 : com47 com48 : com73 com74 : com79 icons icons com0 : com6 com7 : com32 com33 : com39 remapped com scan direction [command: c8] remapped com scan direction [command: c8] c o m 7 3 : : c o m 7 9 i c o n s c o m 3 9 : : c o m 3 3 c o m 3 2 remapped com scan direction [command: c8] remapped com scan direction [command: c8] e see application notes on p.35 five captacitors and four optional resistors for large loading panel. see description on p.15
ssd1820a/21 34 rev 1.4 01/03 solomon application circuit: 4x booster, bias divider disabled. ssd1821 die (die face up) seg0 -------------------------------- seg127 display panel size 128 x 80 + 2 icon lines 80 mux segment remapped [command: a1] remapped com scan direction [command: c8] optional for external resistors gain control [intrs pulled to vss] nc com6 com7 : : : com20 com19 : : : com30 com31 nc c o m 4 6 c o m 4 5 c o m 4 4 c o m 4 3 c o m 4 2 c o m 4 1 c o m 4 0 s e g 1 2 7 s e g 1 2 6 : : : : : : : : : : : : s e g 6 4 s e g 6 3 : : : : : : : : : : : : : : : : : : s e g 2 s e g 1 s e g 0 i c o n s c o m 0 c o m 1 c o m 2 c o m 3 c o m 4 c o m 5 nc com47 com48 : : : com52 com53 : : : com71 com72 nc remapped com scan direction [command: c8] com40 : com47 com48 : com73 com74 : com79 icons icons com0 : com6 com7 : com32 com33 : com39 remapped com scan direction [command: c8] remapped com scan direction [command: c8] c o m 7 3 : : c o m 7 9 i c o n s c o m 3 9 : : c o m 3 3 c o m 3 2 remapped com scan direction [command: c8] remapped com scan direction [command: c8] d 0 - d 7 a n d c o n t r o l b u s c1p c1n c3p vcc vss vss 1 m f 1 m f 1 m f 1 m f c2n c2p vdd vl2 vl3 vl4 vl5 vci/vdd=2.7v r1 r2 vl6 vr vci vss res see application notes on p.35
solomon ssd1820a/21 35 rev 1.4 01/03 application circuit: dc-dc converter circuit configuration v ss + v cc 3x converter c 5p c 3p c 1p c 2p c 1n + + c 2n c 4p v ss + v cc 4x converter c 5p c 3p c 1p c 2p c 1n + + + c 2n c 4p *note: capacitor value = 1.0uf to 4.7uf v ss + v cc 5x converter c 5p c 3p c 1p c 2p c 1n + + + c 2n c 4p + v ss + v cc 6x converter c 5p c 3p c 1p c 2p c 1n + + + c 2n c 4p + + v ss + v cc 2x converter c 5p c 3p c 1p c 2p c 1n c 2n c 4p + ssd1820a and ssd1821 ic work from 2x to 5x and 2x to 6x dc-dc converter respectively. for the capactior connections, please refer to below circuit diagrams. note that if the capacitor connection does not match with the software setting of dc-dc converter factor (0x64~0x67), abnormal current consumption will be observed.
ssd1820a/21 36 rev 1.4 01/03 solomon application note 1: esd protection circuit for ssd1820a/21 ic, it is recommended to design a simple protection circuit to prevent from unexpected external interference. this is useful especially the designed product has to go through unexpected electrostatic discharge. figure 1 is an example of the common circuit used. figure 9: additional esd protection circuit figure 9 shows one of the most common connection design of the lcd driver ic and the main microprocessor (mcu) unit, the res pin of the driver is connected directly to one of the port of the mcu. when external charge is brought near the device, or electrostatic charge (a spike), the charge will be induced inside the device and it will discharge by finding its way to the sho rtest path to ground. this discharge sometimes will affect the normal operation of the device, causing data disruption inside ram or internal register s, or even re-initialize / reset the device. the ic design is in-built with a protection circuit (or a diode circuit to the power a nd ground rails), to protect the i/o pins from external charge or spike. since the diode circuit in the ic is very small, the protection o f the circuit is limited. therefore, it is very useful to build an external device to help prevent the disturbance. it is easy to add a capacitor across the res pin, this will have a big improvement on the stability of the driver ic. in addition, more protection can be done by adding a resistor in series, directly in between the res pin of the driver ic and the port of the mcu. this will create a filter (r-c circuit) effect, that will be able to eliminate external noises entering the res pin of the driver ic. the value of the capacitor and resistor used largely depend on the application printed circuit board design. it is recommended t o test and evaluate to find out the best capacitor value for a particular design application. however, for mobile communication de - vices (eg mobile phones), a lot of applications there is a 1nf capacitor placed across the res pin and ground. (port output pin) microproesscor unit s s d 1 8 2 0 a / 2 1 res c r typical value: c = 1000nf; r = 3 ~ 10k ohm;
solomon ssd1820a/21 37 rev 1.4 01/03 notes 1. general tolerance: 0.050mm 2. all chamfer is r0.20 3. material pi: upilex-s 75um+6 thickness adhesive: toray #7100 12um2 thickness cu: fq-vlp 18um flex coating: fs-100 solder resist: ae-70-m11 2614um 4. plating sn: 0.350.05um 5. optional feature for ssl external use only which may be replaced by ?2.0mm hole 6. 4 sprocket holes (19.00mm)for 1 tape ssd1820at tab package dimension (1 of 3) do not scale this drawing
ssd1820a/21 38 rev 1.4 01/03 solomon ssd1820at tab package dimension (2 of 3) do not scale this drawing
solomon ssd1820a/21 39 rev 1.4 01/03 ssd1820at tab package dimension (3 of 3) do not scale this drawing
ssd1820a/21 40 rev 1.4 01/03 solomon ssd1821t tab package dimension (1 of 3) do not scale this drawing notes 1. general tolerance: 0.050mm 2. all chamfer is r0.20 3. material pi: upilex - s 75um+6 thickness adhesive: toray #7100 12 2um thickness cu: fq - vlp 25um 5um flex coating: fs - 100l solder resist: ar - 7100 26 14um general to lerance 0.300mm 4. plating sn: 0.35 0.05um (0.2 0.05um pure tin) 5. optional feature for ssl external use only which may be replaced by ?2.0mm hole 6. 4 sprocket holes (19.00mm) for 1 tape
solomon ssd1820a/21 41 rev 1.4 01/03 ssd1821t tab package dimension (2 of 3) do not scale this drawing
ssd1820a/21 42 rev 1.4 01/03 solomon ssd1821t tab package dimension (3 of 3) do not scale this drawing
ssd1820a/21 solomon systech reserves the right to make changes without further notice to any products herein. solomon systech makes no warra nty, representation or guar- antee regarding the suitability of its products for any particular purpose, nor does solomon systech assume any liability arisin g out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incident al damages. "typical" parameters can and do vary in different applications. all operating parameters, including "typicals" must be validated for each customer applic ation by customer's technical experts. solomon systech does not convey any license under its patent rights nor the rights of others. solomon systech products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to suppo rt or sustain life, or for any other application in which the failure of the solomon systech product could create a situation where personal injury or death may occu r. should buyer purchase or use solomon systech products for any such unintended or unauthorized application, buyer shall indemnify and hold solomon systech and its offices, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fe es arising out of, directly or indi- rectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges th at solomon systech was negligent regarding the design or manufacture of the part.

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